EP4CE6E22 FPGA Core Development Board (Cyclone IV)

You program the FPGA using Altera Quartus Prime software. Connect a USB Blaster cable to the board's 10-pin JTAG header. In Quartus, compile your Verilog or VHDL design into a .sof file, then use the Programmer tool to download it via JTAG. For persistent storage, you can configure the W25Q SPI flash to load the bitstream on power-up. The CH340 provides a separate UART interface for serial communication with your FPGA design after programming.

The board has jumper caps near the I/O pin headers labeled for voltage selection (e.g., 1.2V, 3.3V, 5V). Place a jumper cap on the two pins corresponding to your desired logic level for that I/O bank. Ensure the connected peripheral modules operate at the same voltage to prevent damage. Note that a group of pins on the right side is fixed at 3.3V and is not configurable. Always power off the board before changing jumper settings.

The 50 MHz oscillator typically serves as the primary clock for the FPGA's internal logic and PLLs, enabling high-speed operations. The 27 MHz clock is often used as a reference for video or audio applications, such as VGA signal generation or audio sampling, where standard timings are required. You can select which oscillator to use globally or for specific modules within your FPGA design via the Quartus Pin Planner and clock management IP cores.

Yes, the W25Q flash is connected to the FPGA via SPI pins and can store both the FPGA configuration bitstream and application data. To store user data, you must instantiate an SPI controller in your FPGA design to communicate with the flash, handling commands for reading, writing, and erasing sectors. The CH340 UART can relay data between a PC and the FPGA, which can then be written to the flash. Ensure your design manages the flash's busy status and wear-leveling for robust operation.