Sipeed MAIX-I Module w/o WiFi (RISC-V 64 AIoT, K210)

The module requires a stable 5V ±0.2V power supply connected to its designated power pins, drawing approximately 300mA under typical load. For programming, connect a USB-to-serial adapter (e.g., CP2102) to the module's UART0 TX/RX pins. Use the official Kendryte SDK or MicroPython firmware, flashing via the kflash.py utility with the correct serial port and baud rate (typically 115200). The FPIOA must be configured to map the UART function to the physical pins you are using for communication.

It features a Digital Video Port (DVP) parallel interface supporting camera sensors like the OV2640 with a maximum resolution of 640x480 pixels. For displays, it provides a standard MCU LCD parallel interface (e.g., for SPI or RGB panels). You will need an FPC adapter or breakout board to connect common camera modules or LCDs. The SDK includes drivers for initializing the DVP bus and handling frame capture, which can then be processed directly by the integrated KPU for object detection or classification tasks.

First, train or obtain a quantized TensorFlow Lite model compatible with the K210's KPU constraints (e.g., specific layer types and parameter limits). Use the official NNCase compiler toolchain from Sipeed to convert the .tflite file into a .kmodel format. Flash this .kmodel to the module's external flash memory. In your C or MicroPython application, load the model using the KPU API, pass image data from the DVP camera (pre-processed to the correct dimensions), and call the KPU inference function to get classification or detection results on the edge.

The Field Programmable IO Array (FPIOA) is a unique hardware peripheral on the K210 that allows you to assign any of 255 internal functions (UART, SPI, I2C, GPIO, etc.) to any of the 48 physical GPIO pins. Configuration is done in software at initialization. For example, to set pin 3 as a UART TX, you call the FPIOA function to map the UART1_TX internal io number to physical pin 3. This provides immense flexibility for board design but requires careful pin planning in your firmware's setup code before using any peripheral.